HD64F7051SFJ20V Datasheet, PDF (133/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 8 Bus State Controller (BSC)
8.1.3 Pin Configuration
Table 8.1 shows the bus state controller pin configuration.
Table 8.1 Pin Configuration
Signal
I/O Description
A21–A0
O
Address output
D15–D0
I/O 16-bit data bus.
CS0–CS3 O
Chip select, indicating the area being accessed
RD
O
Strobe that indicates the read cycle for ordinary space/multiplex I/O.
WRH
O
Strobe that indicates a write cycle to the 3rd byte (D15–D8) for ordinary
space/multiplex I/O. Also output during DRAM access.
WRL
O
Strobe that indicates a write cycle to the least significant byte (D7–D0) for
ordinary space/multiplex I/O. Also output during DRAM access.
WAIT
I
Wait state request signal
BREQ
I
Bus release request input
BACK
O
Bus use enable output
Note: When an 8-bit bus width is selected for external space, WRL is enabled.
When a 16-bit bus width is selected for external space, WRH and WRL are enabled.
8.1.4 Register Configuration
The BSC has eight registers. These registers are used to control wait states, bus width, and
interfaces with memories like ROM and SRAM, as well as refresh control. The register
configurations are listed in table 8.2.
All registers are 16 bits. All BSC registers are all initialized by a power-on reset, but are not by a
manual reset. Values are maintained in standby mode.
Rev. 5.00 Jan 06, 2006 page 111 of 818
REJ09B0273-0500