HD64F7051SFJ20V Datasheet, PDF (83/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 5 Exception Processing
Section 5 Exception Processing
5.1 Overview
5.1.1 Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority shown in table 5.1. When several exception processing sources occur at once,
they are processed according to the priority shown.
Table 5.1 Types of Exception Processing and Priority Order
Exception Source
Priority
Reset
Power-on reset
High
Address
error
CPU address error
DMAC address error
Interrupt
NMI
User break
IRQ
On-chip peripheral modules: • Direct memory access controller
(DMAC)
• Advanced timer unit (ATU)
• Compare match timer (CMT)
• A/D converter (A/D)
• Serial communications interface
(SCI)
• Watchdog timer (WDT)
Instructions Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay Low
branch instruction^*1 or instructions that rewrite the PC^*2)
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF.
Rev. 5.00 Jan 06, 2006 page 61 of 818
REJ09B0273-0500