HD64F7051SFJ20V Datasheet, PDF (178/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 9 Direct Memory Access Controller (DMAC)
Transfer on channel 0
Initial priority setting _{CH0 > CH1 > CH2 > CH3}
Channel 1 is given the lowest
priority.
Priority after transfer
CH1 > CH2 > CH3 > CH0
Transfer on channel 1
Initial priority setting
Priority after transfer
CH0 > CH1 > CH2 > CH3
CH2 > CH3 > CH0 > CH1
When channel 1 is given the
lowest priority, the priority
of channel 0, which was
above channel 1, is also shifted
simultaneously.
Transfer on channel 2
Initial priority setting CH0 > CH1 > CH2 > CH3
Priority after transfer
CH3 > CH0 > CH1 > CH2
Priority after transfer
due to issue of a transfer
request for channel 1
only.
CH2 > CH3 > CH0 > CH1
When channel 2 receives the
lowest priority, the priorities
of channel 0 and 1, which
were above channel 2, are also
shifted simultaneously. Immedi-
ately thereafter, if there is a transfer
request for channel 1 only, channel
1 is given the lowest priority,
and the priorities of channels 3
and 0 are simultaneously
shifted down.
Transfer on channel 3
Initial priority setting _{CH0 > CH1 > CH2 > CH3}
No change in priority.
Priority after transfer _{CH0 > CH1 > CH2 > CH3}
Figure 9.3 Round Robin Mode
Rev. 5.00 Jan 06, 2006 page 156 of 818
REJ09B0273-0500