HD64F7051SFJ20V Datasheet, PDF (475/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 14 A/D Converter
φ
Address
Internal write
signal
Analog input
sampling signal
A/D converter
A/D conversion time (t_CONV)
A/D conversion start
delay time (t_D)
Analog input
sampling time
(t_SPL)
Write cycle
A/D synchronization time
(3 states) (to 14 states)
ADST write timing
Idle
Sample-and-hold A/D conversion
ADF
Figure 14.5 A/D Conversion Timing
End of A/D
conversion
Rev. 5.00 Jan 06, 2006 page 453 of 818
REJ09B0273-0500