HD64F7051SFJ20V Datasheet, PDF (833/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
Reset
Power-Down State
Type
Registers
(Abbreviations)
Power-
On
Hardware Software
Standby Standby Sleep
I/O ports
PADR, PBDR, PCDR, Initialized Initialized Held
PDDR, PEDR, PFDR,
PGDR, PHDR
Held
Flash ROM
FLMCR1
Initialized Initialized Initialized Held
FLMCR2
Held
EBR1
Initialized
RAMER
Held
Power-down state
related
SBYCR
SYSCR
Initialized Initialized Held
Held
Note: * Bits 7 to 5 (OVF, WT/IT, and TME) are initialized, and bits 2 to 0 (CKS2 to CKS0) are
held.
Rev. 5.00 Jan 06, 2006 page 811 of 818
REJ09B0273-0500