HD64F7051SFJ20V Datasheet, PDF (360/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Input Capture Operation when Free-Running Counter is Halted: In channel 0 or channels 1
to 5, if input capture setting is performed and a trigger signal is input from the input pin, the
TCNT value will be transferred to the corresponding general register (GR) or input capture
register (ICR) irrespective of whether the free-running counter (TCNT) is running or halted, and
the IMF or ICF bit will be set in the timer status register (TSR).
The timing in this case is shown in figure 10.62
CK
Timer status register
TSR
Internal input capture
signal
TCNT
N
GR (ICR)
N
Interrupt status flag
IMF (ICF)
Figure 10.62 Input Capture Operation before Free-Running Counter is Started
Rev. 5.00 Jan 06, 2006 page 338 of 818
REJ09B0273-0500