HD64F7051SFJ20V Datasheet, PDF (720/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
Bit Bit Name
4 Framing error
(FER)
3 Parity error (PER)
2 Transmit end
(TEND)
1 Multiprocessor bit
(MPB)
0 Multiprocessor bit
transfer (MPBT)
Value Description
0
Receiving in progress, or completed normally
(Initial value)
[Clearing conditions]
1. Power-on reset, or transition to hardware standby mode or software
standby mode
2. Read FER when FER = 1, then write 0 in FER
1
Framing error occurred during reception
[Setting condition]
Framing error (stop bit is 0)
0
Receiving in progress, or completed normally
(Initial value)
[Clearing conditions]
1. Power-on reset, or transition to hardware standby mode or software
standby mode
2. Read PER when PER = 1, then write 0 in PER
1
Parity error occurred during reception
[Setting condition]
Parity error (parity of receive data does not match parity setting of O/E bit
in SMR)
0
Transmitting in progress
[Clearing conditions]
1. Read TDRE when TDRE = 1, then write 0 in TDRE
2. The DMAC writes data in TDR
1
Transmitting has ended
(Initial value)
[Setting conditions]
1. Power-on reset, or transition to hardware standby mode or software
standby mode
2. TE is cleared to 0 in SCR
3. TDRE = 1 when last bit of 1-byte serial transmit character is
transmitted
0
Multiprocessor bit value in receive data is 0
(Initial value)
1
Multiprocessor bit value in receive data is 1
0
Multiprocessor bit value in transmit data is 0
(Initial value)
1
Multiprocessor bit value in transmit data is 1
Rev. 5.00 Jan 06, 2006 page 698 of 818
REJ09B0273-0500