HD64F7051SFJ20V Datasheet, PDF (487/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 15 Compare Match Timer (CMT)
15.2.4 Compare Match Timer Constant Register (CMCOR)
The compare match timer constant register (CMCOR) is a 16-bit register that sets the compare
match period with the CMCNT.
The CMCOR is initialized to H'FFFF by a power-on reset and in hardware standby mode and
software standby mode. There is no initializing with manual reset.
Bit: 15
14
13
12
11
10
9
8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
15.3 Operation
15.3.1 Period Count Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the compare match constant register (CMCOR), the
CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the
CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is
requested. The CMCNT counter begins counting up again from H'0000.
Figure 15.2 shows the compare match counter operation.
Rev. 5.00 Jan 06, 2006 page 465 of 818
REJ09B0273-0500