HD64F7051SFJ20V Datasheet, PDF (362/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Contention between DSTR Bit Setting by CPU and Clearing by Underflow: If underflow
occurs in the T2 state of a down-counter start register (DSTR) “1” write cycle by the CPU,
clearing to 0 by the underflow has priority, and the corresponding bit of DSTR is not set to 1.
The timing in this case is shown in figure 10.64.
STR write cycle
T1
T2
CK
Address
Internal write signal
DSTR address
1 written
to DSTR
DCNT 0001
0000
0000
Underflow signal
Down-count start
register
Figure 10.64 Contention between DSTR Bit Setting by CPU and Clearing by Underflow
Rev. 5.00 Jan 06, 2006 page 340 of 818
REJ09B0273-0500