HD64F7051SFJ20V Datasheet, PDF (810/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
A/D Control Register 1 (ADCR1)
H'FFFF85F9
Bit: 7
6
5
4
3
Bit name: TRGE —
—
—
—
Initial value: 0
1
1
1
1
R/W: R/W
R
R
R
R
8/16
2
1
—
—
1
1
R
R
A/D
0
—
1
R
Bit
Bit Name
Value Description
7
Trigger enable (TRGE) 0
Starting of A/D conversion by external trigger or
ATU trigger is disabled
(Initial value)
1
Starting of A/D conversion by external trigger or
ATU trigger is enabled
User Break Address Register H
(UBARH)
H'FFFF8600
8/16/32
UBC
Bit:
Bit name:
Initial value:
R/W:
15
UBA31
0
R/W
14
UBA30
0
R/W
13
UBA29
0
R/W
12
UBA28
0
R/W
11
UBA27
0
R/W
10
UBA26
0
R/W
9
UBA25
0
R/W
8
UBA24
0
R/W
Bit:
Bit name:
Initial value:
R/W:
7
UBA23
0
R/W
6
UBA22
0
R/W
5
UBA21
0
R/W
4
UBA20
0
R/W
3
UBA19
0
R/W
2
UBA18
0
R/W
1
UBA17
0
R/W
0
UBA16
0
R/W
Bit
15–0
Bit Name
User break address 31 to 16
(UBA31 to UBA16)
Description
Upper half (bits 31 to 16) of the address taken as
the break condition
Rev. 5.00 Jan 06, 2006 page 788 of 818
REJ09B0273-0500