HD64F7051SFJ20V Datasheet, PDF (118/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 7 User Break Controller (UBC)
7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the UBC.
Module bus
Bus
interface
UBBR
UBAMRH
UBAMRL
UBARH
UBARL
Break condition comparator
User break
interrupt
generating
circuit
UBC
UBARH, UBARL: User break address registers H, L
UBAMRH, UBAMRL: User break address mask registers H, L
UBBR: User break bus cycle register
Interrupt request
Interrupt controller
Figure 7.1 User Break Controller Block Diagram
Rev. 5.00 Jan 06, 2006 page 96 of 818
REJ09B0273-0500