HD64F7051SFJ20V Datasheet, PDF (750/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
Timer Interrupt Enable Register C
(TIERC)
H'FFFF82C8 (Channel 2) 8
ATU
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
— OVE2 IME2B IME2A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
Bit
Bit Name
Value Description
2
Overflow interrupt enable 0
OVI2 interrupt requested by OVF2 flag is disabled
(OVE2)
(Initial value)
1
OVI2 interrupt requested by OVF2 flag is enabled
1
Input capture/compare 0
IMI2B interrupt requested by IMF2B flag is
match interrupt enable
disabled
(Initial value)
(IME2B)
1
IMI2B interrupt requested by IMF2B flag is enabled
0
Input capture/compare 0
IMI2A interrupt requested by IMF2A flag is
match interrupt enable
disabled
(Initial value)
(IME2A)
1
IMI2A interrupt requested by IMF2A flag is enabled
Rev. 5.00 Jan 06, 2006 page 728 of 818
REJ09B0273-0500