HD64F7051SFJ20V Datasheet, PDF (752/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
General Registers 2A, 2B
(GR2A, GR2B)
H'FFFF82CC (Channel 2, 2A) 16
H'FFFF82CE (Channel 2, 2B) 16
ATU
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15–0
Bit Name
(Dual-function input capture/output
compare register)
Description
1. Input capture register: Stores TCNT2 value
when input capture signal is generated
2. Output compare register: Set with compare
match value
General Registers 1A to 1F
(GR1A to GR1F)
H'FFFF82D2 (Channel 1, 1A) 16
H'FFFF82D4 (Channel 1, 1B) 16
H'FFFF82D6 (Channel 1, 1C) 16
H'FFFF82D8 (Channel 1, 1D) 16
H'FFFF82DA (Channel 1, 1E) 16
H'FFFF82DC (Channel 1, 1F) 16
ATU
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15–0
Bit Name
(Dual-function input capture/output
compare register)
Description
1. Input capture register: Stores TCNT1 value
when input capture signal is generated
2. Output compare register: Set with compare
match value
Rev. 5.00 Jan 06, 2006 page 730 of 818
REJ09B0273-0500