HD64F7051SFJ20V Datasheet, PDF (270/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Bit 0—Input Capture/Compare-Match Flag (IMF5A): Status flag that indicates GR5A input
capture or compare-match.
Bit 0:
IMF5A
0
1
Description
[Clearing condition]
(Initial value)
When IMF5A is read while set to 1, then 0 is written in IMF5A
[Setting conditions]
• When the TCNT5 value is transferred to GR5A by an input capture signal while
GR5A is functioning as an input capture register
• When TCNT5 = GR5A while GR5A is functioning as an output compare register
Timer Status Register E (TSRE)
TSRE indicates the status of channel 6 to 9 cycle register compare-matches.
Bit: 7
6
5
4
3
2
1
0
— CMF6 — CMF7 — CMF8 — CMF9
Initial value: 0
0
0
0
0
0
0
0
R/W: R R/(W)* R R/(W)* R R/(W)* R R/(W)*
Note: * Only 0 can be written, to clear the flag.
Bit 7—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 6—Cycle Register Compare-Match Flag (CMF6): Status flag that indicates CYLR6
compare-match.
Bit 6:
CMF6
0
1
Description
[Clearing conditions]
• When CMF6 is read while set to 1, then 0 is written in CMF6
• When cleared by the DMAC after data transfer when used as a
DMAC activation source
[Setting condition]
When TCNT6 = CYLR6
(Initial value)
Rev. 5.00 Jan 06, 2006 page 248 of 818
REJ09B0273-0500