HD64F7051SFJ20V Datasheet, PDF (407/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 13 Serial Communication Interface (SCI)
The BRR setting is calculated as follows:
Asynchronous mode:
φ
N=
64 × 2^2n−1 × B
× 10⁶ − 1
Synchronous mode:
φ
N = _{8 × 22n−1 × B}
× 10⁶ − 1
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the following table for the clock sources and value of n.)
SMR Settings
n
Clock Source
CKS1
CKS2
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is calculated as follows:
Error (%) =
φ × 10⁶
(N + 1) × B × 64 × 2^{2n−1 − 1 × 100}
Rev. 5.00 Jan 06, 2006 page 385 of 818
REJ09B0273-0500