HD64F7051SFJ20V Datasheet, PDF (588/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 18 ROM (128 kB Version)
H'000000
Flash memory
EB0 to EB3
H'01F000
EB4
H'01F400
EB5
H'01F800
EB6
H'01FC00
H'01FFFF
EB7
This area can be accessed
from both the RAM area
and flash memory area
H'FFFFE800
H'FFFFEBFF
On-chip RAM
Figure 18.11 Example of RAM Overlap Operation
Example in Which Flash Memory Block Area (EB4) is Overlapped
1. Set bits RAMS, RAM1, and RAM0 in RAMER to 1, 0, 1, to overlap part of RAM onto the
area (EB4) for which real-time programming is required.
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB4).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
regardless of the value of RAM1 and RAM0 (emulation protection). In this state,
setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a
transition to program mode or erase mode. When actually programming a flash
memory area, the RAMS bit should be cleared to 0.
2. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm while flash memory emulation in RAM is being used.
Rev. 5.00 Jan 06, 2006 page 566 of 818
REJ09B0273-0500