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HD64F7051SFJ20V Datasheet, PDF (385/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC
TCNT
value
H'FF
Section 12 Watchdog Timer (WDT)
Overflow
H'00
Time
WT/IT = 1
TME = 1
H'00 written
in TCNT
WOVF = 1 WT/IT = 1
TME = 1
WDTOVF and
internal reset generated
H'00 written
in TCNT
WDTOVF
signal
Internal
reset signal*
128 φ clocks
WT/IT: Timer mode select bit
TME: Timer enable bit
512 φ clocks
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 12.4 Operation in the Watchdog Timer Mode
Rev. 5.00 Jan 06, 2006 page 363 of 818
REJ09B0273-0500