HD64F7051SFJ20V Datasheet, PDF (109/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 6 Interrupt Controller (INTC)
Bits 7 to 0—IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): These bits set the IRQ0–IRQ7
interrupt request detection mode.
Bits 7-0: IRQ0S–IRQ7S
0
1
Description
Interrupt request is detected on low level of IRQ input (initial value)
Interrupt request is detected on falling edge of IRQ input
6.3.3 IRQ Status Register (ISR)
The ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input
pins IRQ0–IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be
withdrawn by writing a 0 to IRQnF after reading an IRQnF = 1.
A power-on reset initializes ISR but the standby mode does not.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
IRQ0F
0
R/W
6
IRQ1F
0
R/W
5
IRQ2F
0
R/W
4
IRQ3F
0
R/W
3
IRQ4F
0
R/W
2
IRQ5F
0
R/W
1
IRQ6F
0
R/W
0
IRQ7F
0
R/W
Bits 15 to 8—Reserved: These bits always read as 0. The write value should always be 0.
Rev. 5.00 Jan 06, 2006 page 87 of 818
REJ09B0273-0500