HD64F7051SFJ20V Datasheet, PDF (159/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 9 Direct Memory Access Controller (DMAC)
9.1.2 Block Diagram
Figure 9.1 is a block diagram of the DMAC.
On-chip ROM
On-chip RAM
On-chip
peripheral
module
DREQ0, DREQ1
ATU
SCI0–SCI2
A/D converter 0, 1
DEIn
DACK0, DACK1
DRAK0, DRAK1
External
ROM
External
RAM
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
DMAC module
Circuit
control
SARn
Register
control
Activation
control
DARn
DMATCRn
CHCRn
Request
priority
control
DMAOR
Bus interface
Bus state
controller
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
DMAOR: DMAC operation register
n: 0, 1, 2, 3
Figure 9.1 DMAC Block Diagram
Rev. 5.00 Jan 06, 2006 page 137 of 818
REJ09B0273-0500