HD64F7051SFJ20V Datasheet, PDF (355/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Contention between Interrupt Status Flag Setting by Interrupt Generation and Clearing: If
an event such as input capture/compare-match or overflow/underflow occurs in the T2 state of an
interrupt status flag 0 write cycle by the CPU, setting of the interrupt status flag to 1 by that event
has priority and the interrupt status flag is not cleared.
The timing in this case is shown in figure 10.57.
TSR write cycle
T1
T2
CK
Address
Internal write signal
TCNT
TSR address
0 written
to TSR
N
N+1
GR
N
Compare-match signal
Interrupt status flag
IMF
Remains unchanged at 1
Figure 10.57 Contention between Interrupt Status Flag Setting by Compare-Match and
Clearing
Rev. 5.00 Jan 06, 2006 page 333 of 818
REJ09B0273-0500