HD64F7051SFJ20V Datasheet, PDF (429/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 13 Serial Communication Interface (SCI)
Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 13.9.
Clock: See the description in the asynchronous mode section.
Example: Sending data H'AA to receiving processor A
Transmitting
processor
Serial communication line
Receiving
processor A
(ID = 01)
Receiving
processor B
(ID = 02)
Receiving
processor C
(ID = 03)
Receiving
processor D
(ID = 04)
Serial
data
H'01
(MPB = 1)
H'AA
(MPB = 0)
ID-transmit cycle:
receiving processor address
MPB: Multiprocessor bit
Data-transmit cycle:
data sent to receiving
processor specified by ID
Figure 13.10 Communication Among Processors Using Multiprocessor Format
Transmitting Multiprocessor Serial Data: Figure 13.11 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the
numbers in the flowchart):
1. SCI initialization: Set the TxD pin using the PFC.
2. SCI status check and transmit data write: Read the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT
(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.
3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it
reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a
transmit-data-empty interrupt request (TxI) to write data in TDR, the TDRE bit is checked and
cleared automatically.
Rev. 5.00 Jan 06, 2006 page 407 of 818
REJ09B0273-0500