HD64F7051SFJ20V Datasheet, PDF (130/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 7 User Break Controller (UBC)
7.5.3 Contention between User Break and Exception Handling
If a user break is set for the fetch of a particular instruction, and exception handling with higher
priority than a user break is in contention and is accepted in the decode stage for that instruction
(or the next instruction), user break exception handling may not be performed after completion of
the higher-priority exception handling routine (on return by RTE).
7.5.4 Break at Non-Delay Branch Instruction Jump Destination
When a branch instruction with no delay slot (including exception handling) jumps to the jump
destination instruction on execution of the branch, a user break will not be generated even if a user
break condition has been set for the first jump destination instruction fetch.
Rev. 5.00 Jan 06, 2006 page 108 of 818
REJ09B0273-0500