HD64F7051SFJ20V Datasheet, PDF (723/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
Timer Interrupt Enable Register DH H'FFFF8202
8
ATU
(TIERDH)
(Channels 3 to 5)
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
— OVE3 IME3D IME3C IME3B IME3A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W R/W R/W R/W R/W
Bit
Bit Name
Value Description
4
Overflow interrupt enable 0
OVI3 interrupt requested by OVF3 flag is disabled
(OVE3)
(Initial value)
1
OVI3 interrupt requested by OVF3 flag is enabled
3
Input capture/compare 0
IMI3D interrupt requested by IMF3D flag is
match interrupt enable
disabled
(Initial value)
(IME3D)
1
IMI3D interrupt requested by IMF3D flag is enabled
2
Input capture/compare 0
IMI3C interrupt requested by IMF3C flag is
match interrupt enable
disabled
(Initial value)
(IME3C)
1
IMI3C interrupt requested by IMF3C flag is enabled
1
Input capture/compare 0
IMI3B interrupt requested by IMF3B flag is
match interrupt enable
disabled
(Initial value)
(IME3B)
1
IMI3B interrupt requested by IMF3B flag is enabled
0
Input capture/compare 0
IMI3A interrupt requested by IMF3A flag is
match interrupt enable
disabled
(Initial value)
(IME3A)
1
IMI3A interrupt requested by IMF3A flag is enabled
Rev. 5.00 Jan 06, 2006 page 701 of 818
REJ09B0273-0500