HD64F7051SFJ20V Datasheet, PDF (184/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 9 Direct Memory Access Controller (DMAC)
CK
A21–A0
CSn
D15–D0
RD
WRH, WRL
DACK
Transfer source
address
Transfer destination
address
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: Transfer between external memories with DACK are output during read
cycle.
Figure 9.8 Direct Address Transfer Timing in Dual Address Mode
Rev. 5.00 Jan 06, 2006 page 162 of 818
REJ09B0273-0500