HD64F7051SFJ20V Datasheet, PDF (56/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 2 CPU
Instruction Formats
nm format
15
0
xxxx nnnn mmmm xxxx
md format
15
0
xxxx xxxx mmmm dddd
nd4 format
15
xxxx xxxx
0
nnnn dddd
nmd format
15
0
xxxx nnnn mmmm dddd
Source
Operand
mmmm: Direct
register
mmmm: Direct
register
mmmm: Indirect
post-increment
register
(multiply/
accumulate)
nnnn^*: Indirect
post-increment
register
(multiply/
accumulate)
mmmm: Indirect
post-increment
register
mmmm: Direct
register
mmmm: Direct
register
mmmmdddd:
indirect register
with
displacement
R0 (Direct
register)
Destination
Operand
nnnn: Direct
register
nnnn: Indirect
register
MACH, MACL
Example
ADD Rm,Rn
MOV.L Rm,@Rn
MAC.W
@Rm+,@Rn+
nnnn: Direct
register
MOV.L @Rm+,Rn
nnnn: Indirect
pre-decrement
register
nnnn: Indirect
indexed register
R0 (Direct
register)
MOV.L Rm,@-Rn
MOV.L
Rm,@(R0,Rn)
MOV.B
@(disp,Rm),R0
nnnndddd:
MOV.B
Indirect register R0,@(disp,Rn)
with displacement
mmmm: Direct
register
mmmmdddd:
Indirect register
with
displacement
nnnndddd:
Indirect register
with displacement
nnnn: Direct
register
MOV.L
Rm,@(disp,Rn)
MOV.L
@(disp,Rm),Rn
Rev. 5.00 Jan 06, 2006 page 34 of 818
REJ09B0273-0500