HD64F7051SFJ20V Datasheet, PDF (338/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
10.5.4 Registers Requiring 8-Bit Access
The timer mode register (TMOR), prescaler register 1 (PSCR1), timer I/O control register 0
(TIOR0), the trigger selection register (TGSR), interval interrupt request register (ITVRR), timer
status register (TSR), timer interrupt enable register (TIER), and down-count start register (DSTR)
are 8-bit registers. These registers are connected to the upper 8 bits or lower 8 bits of the internal
16-bit data bus, and can be read or written a byte at a time.
Figures 10.43 and 10.44 show the operation when performing individual byte read or write
accesses to TGSR and TIOR0A.
CPU
Internal data bus
Only upper 8 bits used
Bus
interface
Module data bus
Only upper 8 bits used
Figure 10.43 Byte Read/Write Access to TGSR
TGSR
CPU
Internal data bus
Only lower 8 bits used
Bus
interface
Module data bus
Only lower 8 bits used
Figure 10.44 Byte Read/Write Access to TIORA
TIOR0A
10.6 Sample Setup Procedures
Sample setup procedures for activating the various ATU functions are shown below.
Sample Setup Procedure for Input Capture: An example of the setup procedure for input
capture is shown in figure 10.45.
1. Set the first-stage counter clock φ' in prescaler register 1 (PSCR1).
For channels 1 to 5, also select the second-stage counter clock φ" with the CKSEL bit in the
timer control register (TCR). When selecting an external clock, also select the external clock
edge type with the CKEG bit in TCR.
2. Set the port E control register (PECR) or port G control register (PGCR), corresponding to the
port for signal input as the input capture trigger, to ATU input capture input.
3. Select rising edge, falling edge, or both edges as the input capture signal input edge(s) with the
timer I/O control register (TIOR).
If necessary, an interrupt request can be sent to the CPU on input capture by making the
appropriate setting in the interrupt enable register (TIER).
Rev. 5.00 Jan 06, 2006 page 316 of 818
REJ09B0273-0500