HD64F7051SFJ20V Datasheet, PDF (666/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 21 Power-Down State
21.2 Register Descriptions
21.2.1 Standby Control Register (SBYCR)
The standby control register (SBYCR) is a read/write 8-bit register that sets the transition to
standby mode, and the port status in standby mode. The SBYCR is initialized to H'1F by reset.
Bit: 7
6
5
4
3
2
1
0
SSBY HIZ
—
—
—
—
—
—
Initial value: 0
0
0
1
1
1
1
1
R/W: R/W R/W
R
R
R
R
R
R
Bit 7—Standby (SSBY): Specifies transition to the standby mode. The SSBY bit cannot be set to
1 while the watchdog timer is running (when the timer enable bit (TME) of the WDT timer
control/status register (TCSR) is set to 1). To enter the standby mode, always halt the WDT by 0
clearing the TME bit, then set the SSBY bit.
Bit 7: SSBY
0
1
Description
Executing SLEEP instruction puts the LSI into sleep mode (initial value)
Executing SLEEP instruction puts the LSI into standby mode
Bit 6—Port High Impedance (HIZ): In the standby mode, this bit selects whether to set the I/O
port pin to high impedance or hold the pin status. The HIZ bit cannot be set to 1 when the TME bit
of the WDT timer control/status register (TCSR) is set to 1. When making the I/O port pin status
high impedance, always clear the TME bit to 0 before setting the HIZ bit.
Bit 6: HIZ
0
1
Description
Holds pin status while in standby mode (initial value)
Keeps pin at high impedance while in standby mode
Bits 5–0—Reserved: Bit 5 always reads as 0. Always write 0 to bit 5. Bits 4–0 always read as 1.
Always write 1 to these bits.
Rev. 5.00 Jan 06, 2006 page 644 of 818
REJ09B0273-0500