HD64F7051SFJ20V Datasheet, PDF (749/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
Bit
Bit Name
Value Description
2
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
(IMF1C)
1
Read IMF1C when IMF1C =1, then write 0 in IMF1C
[Setting conditions]
1. TCNT1 value is transferred to GR1C by an input
capture signal when GR1C functions as an input
capture register
2. TCNT1 = GR1C when GR1C functions as an output
compare register
1
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
Read IMF1B when IMF1B =1, then write 0 in IMF1B
(IMF1B)
1
[Setting conditions]
1. TCNT1 value is transferred to GR1B by an input
capture signal when GR1B functions as an input
capture register
2. TCNT1 = GR1B when GR1B functions as an output
compare register
0
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
(IMF1A)
1
Read IMF1A when IMF1A =1, then write 0 in IMF1A
[Setting conditions]
1. TCNT1 value is transferred to GR1A by an input
capture signal when GR1A functions as an input
capture register
2. TCNT1 = GR1A when GR1A functions as an output
compare register
Rev. 5.00 Jan 06, 2006 page 727 of 818
REJ09B0273-0500