HD64F7051SFJ20V Datasheet, PDF (346/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Sample Setup Procedure for Interval Timer Operation: An example of the setup procedure for
interval timer operation is shown in figure 10.50.
1. Set the first-stage counter clock φ' in prescaler register 1 (PSCR1).
2. Set the ITVE0–ITVE3 bit to be used in the interval interrupt request register (ITVRR) to 1. An
interrupt request can be sent to the CPU when the corresponding bit changes to 1 in the
channel 0 free-running counter (TCNT0).
To start A/D converter sampling, set the ITVAD0–ITVAD3 bit to be used in ITVRR to 1.
3. Set bit 0 to 1 in the timer start register (TSTR) to start TCNT0.
Note: TCNT0 bit 10 corresponds to ITVE0 and ITVAD0, bit 11 to ITVE1 and ITVAD1, bit 12
to ITVE2 and ITVAD2, and bit 13 to ITVE3 and ITVAD3.
Start
Select counter clock 1
Set interval
2
Start counter
3
Interrupt request to CPU
or start of A/D0 sampling
Figure 10.50 Sample Setup Procedure for Interval Timer Operation
Rev. 5.00 Jan 06, 2006 page 324 of 818
REJ09B0273-0500