HD64F7051SFJ20V Datasheet, PDF (746/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Appendix A On-Chip Supporting Module Registers
Bit Bit Name
Value
6, 5, 4 I/O control 1B2–IB0, ID2–ID0, 0 0 0
IF2–1F0, 2B2–2B0
(IO1B2–IO1B0, IO1D2–IO1D0,
IO1F2–IO1F0, IO2B2–IO2B0)
1
10
1
100
1
10
1
2, 1, 0 I/O control 1A2–1A0,
000
IC2–IC0, 1E2–1E0, 2A2–2A0
(IO1A2–IO1A0, IO1C2–IO1C0,
IO1E2–IO1E0, IO2A2–IO2A0)
1
10
1
100
1
10
1
Description
GR is output
compare
register
GR is input
capture
register
GR is output
compare
register
GR is input
capture
register
0 output regardless of compare
match
(Initial value)
0 output at GR compare match
1 output at GR compare match
Output toggles at GR compare
match
Input capture disabled
Input capture to GR at rising edge
Input capture to GR at falling
edge
Input capture to GR at both
edges
0 output regardless of compare
match
(Initial value)
0 output at GR compare match
1 output at GR compare match
Output toggles at GR compare
match
Input capture disabled
Input capture to GR at rising edge
Input capture to GR at falling
edge
Input capture to GR at both
edges
Rev. 5.00 Jan 06, 2006 page 724 of 818
REJ09B0273-0500