HD64F7051SFJ20V Datasheet, PDF (71/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 2 CPU
From any state
when RES = 0
Power-on reset state
RES = 0
HSTBY = 1
When an interrupt source
or DMA address error occurs
RES = 1
Exception processing state
Bus request
cleared
Bus request
generated
Bus release state
Exception
processing
source occurs
NMI interrupt
source occurs
Exception
processing
ends
Bus request
generated
Bus request
cleared
Bus request
generated
Bus request
cleared
SBY bit
cleared
for SLEEP
instruction
Program execution state
SBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Hardware standby mode
Power-down state
From any state when
RES = 0 and HSTBY = 0
Figure 2.6 Transitions between Processing States
Rev. 5.00 Jan 06, 2006 page 49 of 818
REJ09B0273-0500