HD64F7051SFJ20V Datasheet, PDF (262/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 10 Advanced Timer Unit (ATU)
Bit 5—Input Capture/Compare-Match Flag (IMF1F): Status flag that indicates GR1F input
capture or compare-match.
Bit 5:
IMF1F
0
1
Description
[Clearing condition]
(Initial value)
When IMF1F is read while set to 1, then 0 is written in IMF1F
[Setting conditions]
• When the TCNT1 value is transferred to GR1F by an input capture signal while
GR1F is functioning as an input capture register
• When TCNT1 = GR1F while GR1F is functioning as an output compare register
Bit 4—Input Capture/Compare-Match Flag (IMF1E): Status flag that indicates GR1E input
capture or compare-match.
Bit 4:
IMF1E
0
1
Description
[Clearing condition]
(Initial value)
When IMF1E is read while set to 1, then 0 is written in IMF1E
[Setting conditions]
• When the TCNT1 value is transferred to GR1E by an input capture signal while
GR1E is functioning as an input capture register
• When TCNT1 = GR1E while GR1E is functioning as an output compare register
Bit 3—Input Capture/Compare-Match Flag (IMF1D): Status flag that indicates GR1D input
capture or compare-match.
Bit 3:
IMF1D
0
1
Description
[Clearing condition]
(Initial value)
When IMF1D is read while set to 1, then 0 is written in IMF1D
[Setting conditions]
• When the TCNT1 value is transferred to GR1D by an input capture signal while
GR1D is functioning as an input capture register
• When TCNT1 = GR1D while GR1D is functioning as an output compare register
Rev. 5.00 Jan 06, 2006 page 240 of 818
REJ09B0273-0500