HD64F7051SFJ20V Datasheet, PDF (823/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

DMAC Operation Register
(DMAOR)
Bit: 15
14
Bit name: —
—
Initial value: 0
0
R/W: R
R
Appendix A On-Chip Supporting Module Registers
H'FFFF86B0
(All Channels)
16
DMAC
13
12
11
10
9
8
—
—
—
—
PR1 PR0
0
0
0
0
0
0
R
R
R
R
R/W R/W
Bit: 7
6
5
4
3
2
1
Bit name: —
—
—
—
—
AE NMIF
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/(W)*
Note: * Only 0 can be written in bits AE and NMIF, after reading 1 from these bits.
0
DME
0
R/W
Bit
Bit Name
Value Description
9, 8
Priority mode 1 and 0 0 0 Fixed priority order (CH0 > CH1 > CH2 > CH3)
(PR1, PR0)
(Initial value)
1 Fixed priority order (CH0 > CH2 > CH3 > CH1)
1 0 Fixed priority order (CH2 > CH0 > CH1 > CH3)
1 Round robin mode
2
Address error flag (AE) 0
No address error, DMA transfer enabled (Initial value)
[Clearing condition]
Read AE when AE =1, then write 0 in AE
1
Address error present, DMA transfer disabled
[Setting condition]
Address error due to DMAC
1
NMI flag (NMIF)
0
No NMI input, DMA transfer enabled (Initial value)
[Clearing condition]
Read NMIF when NMIF =1, then write 0 in NMIF
1
NMI input present, DMA transfer disabled
[Setting condition]
NMI interrupt generated
0
DMAC master enable 0
Operation disabled on all channels
(Initial value)
(DME)
1
Operation enabled on all channels
Rev. 5.00 Jan 06, 2006 page 801 of 818
REJ09B0273-0500