HD64F7051SFJ20V Datasheet, PDF (76/843 Pages) Renesas Technology Corp – Hardware Manual Renesas 32-Bit RISC

Section 4 Clock Pulse Generator (CPG)
4.1.1 Block Diagram
A block diagram of the clock pulse generator is shown in figure 4.1.
CPG
EXTAL
XTAL
Oscillator circuit
PLLV_CC
PLLV_SS
PLLCAP
MD3
MD2
PLL multiplier circuit
Frequency
division
selection
circuit
Multiplier
circuit
f×4
Frequency
divider circuit
f×2
Frequency
divider circuit
f×1
CK
(system clock)
Internal clock
Figure 4.1 Block Diagram of the Clock Pulse Generator
Rev. 5.00 Jan 06, 2006 page 54 of 818
REJ09B0273-0500