SED1354 Datasheet, PDF (98/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 90
Epson Research and Development
Vancouver Design Center
8 Registers
8.1 Register Mapping
The SED1354 registers are all memory mapped. The system must provide the external address
decoding through the CS# and M/R# input pins. When CS# = 0 and M/R# = 0, the registers are
mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is
mapped to AB[5:0] = 000001. See the table below:
Table 8-1: SED1354 Addressing
CS#
M/R#
Access
Register access:
0
0
• REG[00h] is addressed when AB[5:0] = 0
• REG[01h] is addressed when AB[5:0] = 1
• REG[n] is addressed when AB[5:0] = n
0
1
Memory access: the 2M byte display buffer is addressed by
AB[20:0]
1
X
SED1354 not selected
8.2 Register Descriptions
Note
Unless specified otherwise, all register bits are reset to 0 during power up. Reserved bits should
be written 0 when programming unless otherwise noted.
8.2.1 Revision Code Register
Revision Code Register
REG[00h]
Product Code Product Code Product Code Product Code Product Code Product Code Revision
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Code Bit 1
RO
Revision
Code Bit 0
bits 7-2
bits 1-0
Product Code Bits [5:0]
This is a read-only register that indicates the product code of the chip. The product code is 000001.
Revision Code Bits [1:0]
This is a read-only register that indicates the revision code of the chip. The revision code is 00.
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18