SED1354 Datasheet, PDF (109/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 101
b
Pixel Panning Register
REG[18h]
RW
Screen 2
Screen 2
Screen 2
Screen 2
Screen 1
Screen 1
Screen 1
Screen 1
Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
This register is used to control the horizontal pixel panning of screen 1 and screen 2. Each screen
can be independently panned to the left by programming its respective Pixel Panning Bits to a non-
zero value. This value represents the number of pixels panned. The maximum pan value is dependent
on the display mode as shown in the table below.
Table 8-8: Pixel Panning Selection
Number of Bits-Per-Pixel
1
2
4
8
15/16
Screen 2 Pixel Panning Bits Used
Bits [3:0]
Bits [2:0]
Bits [1:0]
Bit 0
---
bits 7-4
bits 3-0
Smooth horizontal panning can be achieved by a combination of this register and the Display Start
Address register. See Section 10, “Display Configuration” on page 116 and SED1354 Programming
Notes and Examples, document number X19A-G-002-xx, Section 4 for details.
Screen 2 Pixel Panning Bits [3:0]
Pixel panning bits for screen 2.
Screen 1 Pixel Panning Bits [3:0]
Pixel panning bits for screen 1.
8.2.5 Clock Configuration Register
Clock Configuration Register
REG[19h]
RW
n/a
n/a
n/a
n/a
n/a
MCLK Divide PCLK Divide PCLK Divide
Select
Select Bit 1 Select Bit 0
bit 2
bits 1-0
MCLK Divide Select
When this bit = 1 the memory clock (MCLK) frequency is half of the input clock frequency. When
this bit = 0 the memory clock frequency is equal to the input clock frequency.
PCLK Divide Select Bits [1:0]
These bits determine the amount of divide from the memory clock to generate the pixel clock (PCLK):
Table 8-9: PCLK Divide Selection
PCLK Divide Select Bits [1:0]
00
01
10
11
MCLK/PCLK Frequency Ratio
1
2
3
4
See Section 11.2, “Frame Rate Calculation” on page 120 for selection of PCLK frequency.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16