SED1354 Datasheet, PDF (71/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.4 Display Interface
7.4.1 Power-On/Reset Timing
T_RESET#
RESET#
LCD ENABLE
(REG[0Dh] bit 0)
LCDPWR
FPFRAME
FPLINE
FPSHIFT
FPDAT[15:0]
DRDY
Page 63
Inactive
t1
t2
Active
Active
Active
Figure 7-17: LCD Panel Power-On/Reset Timing
Table 7-17: LCD Panel Power-On/Reset Timing
Symbol
Parameter
Min Typ
T_RESET# RESET# pulse time
100
t1
LCD Enable bit high to FPLINE, FPSHIFT, FPDAT[15:0], DRDY
active
t2
FPLINE, FPSHIFT, FPDAT[15:0], DRDY active to LCDPWR, on
and FPFRAME active
128
Max
T_FPFRAME + 6T_PCLK
Units
us
ns
Frames
Note
Where T_FPFRAME is the period of FPFRAME and T_PCLK is the period of the pixel clock.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16