SED1354 Datasheet, PDF (75/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.4.4 Single Monochrome 8-Bit Panel Timing
Page 67
FPFRAME
FPLINE
MOD
UD[3:0], LD[3:0]
VDP
VNDP
LINE1 LINE2 LINE3 LINE4
LINE479 LINE480
LINE1 LINE2
FPLINE
MOD
FPSHIFT
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
1-1 1-9
1-2 1-10
1-3 1-11
1-4 1-12
1-5 1-13
1-6 1-14
1-7 1-15
1-8 1-16
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
HDP
HNDP
1-633
1-634
1-635
1-636
1-637
1-638
1-639
1-640
Figure 7-21: Single Monochrome 8-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16