SED1354 Datasheet, PDF (54/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 46
7.2 Clock Input Requirements
Clock Input Waveform
tPWH
VIH
VIL
Epson Research and Development
Vancouver Design Center
tPWL
T_CLKI
Symbol
T_CLKI
T_PCLK
T_MCLK
t_PWH
t_PWL
Figure 7-6: Clock Input Requirements
Table 7-6: Clock Input Requirements
Parameter
Input Clock Period (CLKI)
Pixel Clock Period (PCLK) not shown
Memory Clock Period (MCLK) not shown
Input Clock Pulse Width High (CLKI)
Input Clock Pulse Width Low (CLKI)
Min
Typ
12.5
25
25
45%
45%
Max
55%
55%
Units
ns
ns
ns
T_CLKI
T_CLKI
Note
When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2).
There is no minimum frequency for CLKI.
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18