SED1354 Datasheet, PDF (165/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 25
4. Program the Memory Address Offset Registers. Register [17h] will be set to 0 and register
[16h] will be set to 0xA0.
4.2 Panning and Scrolling
Panning and scrolling are typically used to navigate within an image which is too large to be shown
completely on the display device. Although the image is stored entirely in display buffer, only a
portion is actually visible at any given time.
Panning and scrolling refers to the direction the viewport appears to move. Panning describes the
action where the viewport moves horizontally. When panning to the right the image in the viewport
appears to slide to the left. A pan to the left causes the image to appear as if it’s sliding to the right.
Scrolling describes the up and down motion of the viewport. Scrolling down causes the image to
appear to slide upwards and scrolling up results in an image that appears to slide downwards.
On the SED1354 panning is performed by setting two components: the start address registers
provide a word granularity in movement (more than one pixel) while the pixel panning register
allows panning at the pixel level. Scrolling requires changing only the start address registers.
There is an order these registers should be accessed to provide the smoothest apparent movement
possible. Understanding the sequence of operations performed by the SED1354 will make it
apparent why the order should be followed.
The start address is latched at the beginning of each frame, the pixel panning value is latched
immediately upon being set. Setting the registers in the wrong sequence or at the wrong time will
result in a “tearing” or jitter on the display. The correct sequence for programing these registers is:
1. Wait until just after a vertical non-display period (read register [0Ah] and watch bit 7 for the
non-display status).
2. Update the start address registers.
3. Wait until the next vertical non-display period.
4. Update the pixel paning register.
Note
The SED1354 provides a false indication of vertical non-display period when used with a dual
panel display. In this case it is impossible to identify the false signal from the true non-display
period. The result is that panning operations at less than 15 bpp may exhibit an occasional tear as
the result of updating registers in the wrong order. This effect is barely noticeable at 8 bpp but
becomes pronounced at 4 bpp, and lower, color depths. Setting the registers out of sequence will
make the tear more apparent.
Programming Notes and Examples
Issue Date: 98/10/28
SED1354
X19A-G-002-06