SED1354 Datasheet, PDF (201/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 61
Appendix A Supported Panel Values
A.1 Supported Panel Values
The following tables show related register data for different panels. All the examples are based on
8 bpp, 40MHz pixel clock and 2M bytes of 60 ns EDO-DRAM.
Table 9-1: Passive Single Panel
Passive
4-Bit Single
Register
320X240@60Hz
Monochrome
REG[02h] 0000 0000
REG[03h] 0000 0000
REG[04h] 0010 0111
REG[05h] 0001 0000
REG[08h] 1110 1111
REG[09h] 0000 0000
REG[0Ah] 0000 0001
REG[0Dh] 0000 1101
REG[19h] 0000 0110
REG[24h] 0000 0000
REG[26h] load LUT
REG[27h] 0000 0000
Passive
8-Bit Single
320X240@60Hz
Color
0001 0100
0000 0000
0010 0111
0001 0000
1110 1111
0000 0000
0000 0001
0000 1101
0000 0110
0000 0000
load LUT
0000 0000
Passive
8-Bit Single
640X480@60Hz
Monochrome
0001 0000
0000 0000
0100 1111
0000 0101
1101 1111
0000 0001
0000 0001
0000 1101
0000 0001
0000 0000
load LUT
0000 0000
Passive
8-Bit Single
640X480@60Hz
Color
0001 0100
0000 0000
0100 1111
0000 0101
1101 1111
0000 0001
0000 0001
0000 1101
0000 0001
0000 0000
load LUT
0000 0000
Passive
16-Bit Single
640X480@47Hz
Color
0010 0100
0000 0000
0100 1111
0000 0101
1101 1111
0000 0001
0000 0001
0000 1101
0000 0001
0000 0000
load LUT
0000 0000
Notes
set panel type
set MOD rate
set horizontal display width
set horizontal non-display period
set vertical display height bits 7-0
set vertical display height bits 9-8
set vertical non-display period
set 8 bpp and LCD enable
set MCLK and PCLK divide
set Look-Up Table address to 0
load Look-Up Table
set Look-Up Table to bank 0
Table 9-2: Passive Dual Panel
Register
REG[02h]
REG[03h]
REG[04h]
REG[05h]
REG[08h]
REG[09h]
REG[0Ah]
REG[0Dh]
REG[19h]
REG[1Bh]
REG[24h]
REG[26h]
REG[27h]
Passive
8-Bit Dual
640X480@60Hz
Monochrome
0001 0010
0000 0000
0100 1111
0000 0101
1110 1111
0000 0000
0000 0001
0000 1101
0000 0011
0000 0000
0000 0000
load LUT
0000 0000
Passive
8-Bit Dual
640X480@60Hz
Color
0001 0110
0000 0000
0100 1111
0000 0101
1110 1111
0000 0000
0000 0001
0000 1101
0000 0011
0000 0000
0000 0000
load LUT
0000 0000
Passive
16-Bit Dual
640X480@60Hz
Color
0010 0110
0000 0000
0100 1111
0000 0101
1110 1111
0000 0000
0000 0001
0000 1101
0000 0011
0000 0000
0000 0000
load LUT
0000 0000
Notes
set panel type
set MOD rate
set horizontal display width
set horizontal non-display period
set vertical display height bits 7-0
set vertical display height bits 9-8
set vertical non-display period
set 8 bpp and LCD enable
set MCLK and PCLK divide
enable half frame buffer
set Look-Up Table address to 0
load Look-Up Table
set Look-Up Table to bank 0
Programming Notes and Examples
Issue Date: 98/10/28
SED1354
X19A-G-002-06