SED1354 Datasheet, PDF (51/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 43
Table 7-4: Generic MPU Interface Synchronous Timing
Symbol
Parameter
Min
Max
Units
T_BCLK
t1
Bus clock period
A[20:0], M/R#, CS#, RD0#,RD1#,WE0#,WE1# hold time
25
ns
1
ns
t2
A[20:0], M/R#, CS#, RD0#,RD1#,WE0#,WE1# setup time
5
ns
t3
RD0#,RD1#,WE0#,WE1# high to A[20:0], M/R# invalid and CS# high
t4¹
RD0#,RD1#,WE0#,WE1# low and CS# low to WAIT# driven low
0
ns
1
7
ns
t5
BCLK to WAIT# high
0
15
ns
t6
RD0#,RD1#,WE0#,WE1# high to WAIT# high impedance
1
6
ns
t7
D[15:0] valid to second BCLK where RD0#,RD1#,WE0#,WE1# low and CS#
5
ns
low (write cycle)
t8
D[15:0] hold from WE0#, WE1# high (write cycle)
t9²
RD0#,RD1# low to D[15:0] driven (read cycle)
0
ns
3
15
ns
t10
D[15:0] valid to WAIT# high (read cycle)
0
t11
RD0#, RD1# high to D[15:0] high impedance (read cycle)
2
10
1. If the SED1354 host interface is disabled, the timing for WAIT# driven low is relative to the
falling edge of CS# and RD0#, RD1#, WE0#, WE1# or the first positive edge of BCLK after
A[20:0] and M/R# become valid, whichever occurs later.
2. If the SED1354 host interface is disabled, the timing for D[15:0] driven is relative to the falling
edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0] and M/R# become
valid, whichever occurs later.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16