SED1354 Datasheet, PDF (33/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 25
5.4.2 Memory Interface
Table 5-2: Memory Interface Pin Descriptions
Pin Name Type
Pin #
F0A
F1A
F2A
Driver ^{Reset = 0}
Value
Description
This pin has multiple functions.
• For dual CAS# DRAM, this is the column address strobe for
the lower byte (LCAS#).
LCAS# O
50
56
CO1
Output 1 • For single CAS# DRAM, this is the column address strobe
(CAS#).
See Table 5-10: “Memory Interface Pin Mapping,” on page 32
for summary.
This pin has multiple functions.
• For dual CAS# DRAM, this is the column address strobe for
the upper byte (UCAS#).
UCAS# O
49
55
CO1
Output 1 • For single CAS# DRAM, this is the write enable signal for the
upper byte (UWE#).
See Table 5-10: “Memory Interface Pin Mapping,” on page 32
for summary.
This pin has multiple functions.
• For dual CAS# DRAM, this is the write enable signal (WE#).
WE#
O
48
54
CO1
Output 1
• For single CAS# DRAM, this is the write enable signal for the
lower byte (LWE#).
See Table 5-10: “Memory Interface Pin Mapping,” on page 32
for summary.
RAS# O
47
53
CO1
Output 1 Row address strobe.
MD[15:0] IO
67, 65,
63, 61,
59, 57,
55, 53,
52, 54,
56, 58,
60, 62,
64, 66
76, 70,
68, 66,
64, 62,
60, 58,
59, 61,
63, 65,
67, 69,
75, 77
These pins have multiple functions.
• Bi-directional memory data bus.
• During reset, these pins are inputs and their states at the
CD2/TS1
Hi-Z
(pulled 0)
rising edge of RESET# are used to configure the chip.
Internal pull-down resistors (typical values of
100KΩ/100KΩ/120KΩ at 5.0V/3.3V/3.0V respectively) pull
the reset states to 0. External pull-up resistors can be used
to pull the reset states to 1. See Section 5.5, “Summary of
Configuration Options” on page 31.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16