SED1354 Datasheet, PDF (120/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 112
Epson Research and Development
Vancouver Design Center
8.2.9 External RAMDAC Control Registers
Note
1. In a Little-Endian architecture, the RAMDAC should be connected to the low byte of the
CPU data bus and the following registers are accessed at the lower address given for
each register (28h, 2Ah, 2Ch, and 2Eh).
In a Big-Endian architecture, the RAMDAC should be connected to the high byte of the
CPU data bus and the following registers are accessed at the higher address given for
each register (29h, 2Bh, 2Dh, and 2Fh).
2. When accessing the External RAMDAC Control registers with either of the architectures
described in note 1, accessing the adjacent unused registers is prohibited.
3. To access the RAMDAC registers the CRT enable bit, REG[0Dh] bit 1, must be set to 1.
RAMDAC Pixel Read Mask Register
REG[28h] or REG[29h]
RAMDAC
Data Bit 7
RAMDAC
Data Bit 6
RAMDAC
Data Bit 5
RAMDAC
Data Bit 4
RAMDAC
Data Bit 3
RAMDAC
Data Bit 2
RAMDAC
Data Bit 1
RW
RAMDAC
Data Bit 0
bits 7-0
RAMDAC Pixel Read Mask Bits [7:0]
A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 1
and DACRS0 = 0 to the external RAMDAC for a pixel read mask register access. The RAMDAC
data must be transferred directly between the system data bus and the external RAMDAC through
either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
RAMDAC Read Mode Address Register
REG[2Ah] or REG[2Bh]
RW
RAMDAC
RAMDAC
RAMDAC
RAMDAC
RAMDAC
RAMDAC
RAMDAC
RAMDAC
Address Bit 7 Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0
bits 7-0
RAMDAC Read Mode Address Bits [7:0]
A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 1
and DACRS0 = 1 to the external RAMDAC for a read-mode address register access. The RAM-
DAC address must be transferred directly between the system data bus and the external RAMDAC
through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian
system.
RAMDAC Write Mode Address Register
REG[2Ch] or REG[2Dh]
RW
RAMDAC
RAMDAC
RAMDAC
RAMDAC
RAMDAC
RAMDAC
RAMDAC
RAMDAC
Address Bit 7 Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0
bits 7-0
RAMDAC Write Mode Address Bits [7:0]
A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 0
and DACRS0 = 0 to the external RAMDAC for a write-mode address register access. The RAM-
DAC address must be transferred directly between the system data bus and the external RAMDAC
through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian
system.
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18