SED1354 Datasheet, PDF (96/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 88
Epson Research and Development
Vancouver Design Center
Table 7-29: CRT A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Parameter
DACCLK period
DACCLK pulse width high
DACCLK pulse width low
data setup to DACCLK rising edge
data hold from DACCLK rising edge
HRTC cycle time
HRTC pulse width (shown active low)
VRTC cycle time
VRTC pulse width (shown active low)
horizontal display period
HRTC setup to DACCLK rising edge
Min
Typ
Max
Units
1
Ts (note 1)
0.45
Ts
0.45
Ts
0.45
Ts
0.45
Ts
note 2
note 3
note 4
note 5
note 6
0.45
Ts
t12
VRTC falling edge to FPLINE falling edge
phase difference
note 7
t13
BLANK# to DACCLK rising edge setup time
0.45
Ts
t14
BLANK# pulse width
note 8
t15
BLANK# falling edge to HRTC falling edge
note 9
t16
BLANK# hold from DACCLK rising edge
0.45
Ts
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t6_min = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts
3. t7_min = [((REG[07h] bits [3:0])+1)*8] Ts
4. t8 _min = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [6:0])+1)] lines
5. t9_min = [((REG[0Ch] bits [2:0])+1)] lines
6. t10_min = [((REG[04h] bits [6:0])+1)*8] Ts
7. t12_min = [((REG[06h] bits [4:0])+1)*8] Ts
8. t14_min = [((REG[04h] bits [6:0])+1)*8] Ts
9. t15_min = [((REG[06h] bits [4:0])+1)*8 - 2] Ts
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18