SED1354 Datasheet, PDF(150/472 Page) Epson Company – Color Graphics LCD/CRT Controller

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SED1354 Datasheet, PDF (150/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

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Page 10

Epson Research and Development

Vancouver Design Center

2.2.2 Initialization Example

This section presents an example of how to initialize the SED1354 registers.

Example 1: Initialize the registers for a 16 color 640x480 dual passive LCD using a 16 bit

data interface; assume 2M byte of display buffer.

Program the SED1354 registers in the following order with the data supplied. Note that for this

example, it is assumed that the arrays âunsigned char RED[16], GREEN[16], BLUE[16]â are

defined and initialized for the required colors. For example, RED[2], GREEN[2], and BLUE[2] refer

to the color components of pixel value 2.

In addition, it is assumed that there is no external RAMDAC since only the LCD is being

programmed. Consequently, the RAMDAC registers are not programmed.

For code examples, see Section 9, âSample Codeâ on page 54.

Table 2-1: Initializing the SED1354 Registers

Operation

REG[1Bh] = 0x00

REG[23h] = 0x80

REG[01h] = 0x30

REG[22h] = 0x24

REG[02h] = 0x26

REG[03h] = 0x00

REG[04h] = 0x4F

REG[05h] = 0x1F

REG[06h] = 0x00

REG[07h] = 0x00

REG[08h] = 0xEF

REG[09h] = 0x00

REG[0Ah] = 0x01

REG[0Bh] = 0x00

REG[0Ch] = 0x00

REG[0Eh] = 0xFF

REG[0Fh] = 0x03

REG[10h] = 0x00

REG[11h] = 0x00

REG[12h] = 0x00

REG[13h] = 0x00

REG[14h] = 0x00

REG[15h] = 0x00

REG[16h] = 0xA0

REG[17h] = 0x00

REG[18h] = 0x00

REG[19h] = 0x01

REG[1Ah] = 0x00

REG[1Eh] = 0x00

REG[1Fh] = 0x00

Description

Enable Host Interface

Disable the Display FIFO

Set Memory Type

Set Performance Register

Set Dual/Single Panel

MOD Rate

Horizontal Display Width

Horizontal Non-Display Period

HSYNC Start Position

HSYNC Pulse Width

Vertical Display Height

Vertical Non-Display Period

VSYNC Start Position

VSYNC Pulse Width

Screen 1 Line Compare

Screen 1 Display Start Address

Screen 2 Display Start Address

Memory Address Offset

Pixel Panning

Clock Configuration

Power Save Configuration

General I/O Configuration

SED1354

X19A-G-002-06

Programming Notes and Examples

Issue Date: 98/10/28

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