SED1354 Datasheet, PDF (166/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 26
Epson Research and Development
Vancouver Design Center
4.2.1 Registers
REG[10h] Screen 1 Display Start Address 0
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[11h] Screen 1 Display Start Address 1
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
REG[12h] Screen 1 Display Start Address 2
n/a
n/a
n/a
n/a
Start Address Start Address Start Address Start Address
Bit 19
Bit 18
Bit 17
Bit 16
These three registers form the address of the word in the display buffer where screen 1 will start
displaying from. Changing these registers by one will cause a change of 0 to 16 pixels depending on
the current color depth. Refer to the following table to see the minimum number of pixels affected
by a change of one to these registers.
Table 4-1: Number of Pixels Panned Using Start Address
Color Depth (bpp) Pixels per Word
1
16
Number of Pixels Panned
16
2
8
8
4
4
4
8
2
2
15
1
1
16
1
1
REG[18h] Pixel Panning Register
Screen 2
Pixel Pan
Bit 3
Screen 2
Pixel Pan
Bit 2
Screen 2
Pixel Pan
Bit 1
Screen 2
Pixel Pan
Bit 0
Screen 1
Pixel Pan
Bit 3
Screen 1
Pixel Pan
Bit 2
Screen 1
Pixel Pan
Bit 1
Screen 1
Pixel Pan
Bit 0
The pixel panning register offers finer control over pixel pans than is available with the Start Address
Registers. Using this register it is possible to pan the displayed image one pixel at a time. Depending
on the current color depth certain bits of the pixel pan register are not used. The following table
shows this.
Table 4-2: Active Pixel Pan Bits
Color Depth (bpp) Pixel Pan bits used
1
bits [3:0]
2
4
8
15/16
bits [2:0]
bits [1:0]
bit 0
---
SED1354
X19A-G-002-06
Programming Notes and Examples
Issue Date: 98/10/28