SED1354 Datasheet, PDF (69/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing
Page 61
t1
Memory
Clock
t2
t3
RAS#
CAS#
t4
t5
t6
Figure 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing
Table 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing
Symbol
Parameter
Min
Typ
t1
Memory clock
40
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00)
2 t1
t2
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10)
1 t1
Random read or write cycle time (REG[22h] bits [6:5] = 00)
5 t1
t3
Random read or write cycle time (REG[22h] bits [6:5] = 01)
4 t1
Random read or write cycle time (REG[22h] bits [6:5] = 10)
3 t1
CAS# precharge time (REG[22h] bits [3:2] = 00)
2 t1
t4
CAS# precharge time (REG[22h] bits [3:2] = 01 or 10)
1 t1
t5
CAS# setup time (CAS# before RAS# refresh)
RAS# precharge time (REG[22h] bits [3:2] = 00)
t6
RAS# precharge time (REG[22h] bits [3:2] = 01 or 10)
0.45 t1 - 2
2.45 t1 - 1
1.45 t1 - 1
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16