SED1354 Datasheet, PDF (399/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
4 MC68328 To SED1354 Interface
Page 11
4.1 Hardware Description
As mentioned earlier in this application note, the MC68328 multiplexes dual functions on
some of its bus control pins, specifically UDS, LDS, and DTACK. If all of these pins are
available for use as bus control pins, then the SED1354 interface is a straightforward imple-
mentation of the MC68000 Bus 1 interface mode as described in the SED1354 Hardware
Functional Specification, document number X19A-A-002-xx. Following are the electrical
connections required for this interface.
MC68328
A21
A[20:1]
D[15:0]
CSB3
DTACK
AS
UDS
LDS
R/W
CLK0
Vcc
470
Vcc
System RESET
SED1354
M/R#
AB[20:1]
SD[15:0]
CS#
WAIT#
BS#
WE1#
AB0
RD1#
RD0#
BUSCLK
RESET#
Note:
When connecting the SED1354 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Block Diagram of MC68328 to SED1354 Interface - MC68000 Bus 1 Interface Mode
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor
Issue Date: 99/04/19
SED1354
X19A-G-013-01