SED1354 Datasheet, PDF (468/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 20
Epson Research and Development
Vancouver Design Center
5.5 SED1354 Configuration
The SED1354 latches MD0 through MD15 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
SED1354 Hardware Specification, document number X19A-A-002-xx.
The partial table below only shows those configuration settings relevant to the IT8368E
implementation.
Table 5-3: SED1354 Configuration using the IT8368E
SED1354
Pin Name
MD0
MD1
MD2
MD3
MD4
MD5
value on this pin at rising edge of RESET# is used to configure:(1/0)
1
0
8-bit host bus interface
16-bit host bus interface
See “Host Bus Selection” table below
See “Host Bus Selection” table below
Little Endian
WAIT# signal is active high
Big Endian
WAIT# signal is active low
= required configuration for connection using ITE IT8368E
MD3
0
0
0
0
1
Table 5-4: SED1354 Host Bus Selection using the IT8368E
MD2
0
0
1
1
x
MD1
0
1
0
1
x
Host Bus Interface
SH-3 bus interface
MC68K bus 1 interface (e.g. MC68000)
MC68K bus 2 interface (e.g. MC68030)
Generic bus interface (e.g. MCF5307, ISA bus interface)
Reserved
= required configuration for connection using ITE IT8368E
SED1354
X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 99/03/10